Embedded electrical interconnects within dielectric substrates find widespread use for various electronic applications. For example, microprocessor integrated circuits generally include numerous levels of interconnect routing in the form of electrical interconnects, such as lines and dots, embedded within a dielectric substrate to connect transistors within the integrated circuits. Each level of interconnect routing is separated from immediately adjacent levels by the dielectric material, referred to in the art as an interlayer dielectric (ILD). The ILD generally includes an oxide layer that includes an oxide, such as silicon dioxide formed from tetraethyl orthosilicate (TEOS), and may include one or more additional layers of dielectric material such as low-k or ultra-low k (ULK) material. Adjacent levels of interconnect routing may be embedded in distinct layers of ILD, and with the interconnect routing configured in such a way so as to ensure that dielectric material separates the adjacent interconnect routings. In this regard, the embedded electrical interconnects in the interconnect routing can be selectively insulated from both other embedded electrical interconnects in the same interconnect routing and from embedded electrical interconnects in interconnect routing of adjacent levels. Likewise, embedded electrical interconnects in adjacent levels of interconnect routing can also be selectively connected to fabricate desired circuitry in the integrated circuits.
With advances in integrated circuits, driven by a desire to shrink sizes, aspect ratios of height to width of the embedded electrical interconnects in the interconnect routing have been maximized to enable spacing between the embedded electrical interconnects to be minimized. However, the minimized spacing between the embedded electrical interconnects gives rise to device reliability concerns that are attributable to various phenomena. One particular phenomena that gives rise to reliability concerns is time dependent dielectric breakdown (TDDB), which results from migration of metal ions from the embedded electrical interconnects into an interface between adjacent levels of the interconnect routing. TDDB is often exacerbated with decreased spacing between embedded electrical interconnects in the interconnect routings. To combat TDDB, efforts have been made to recess the embedded electrical interconnects within the ILD, thereby offsetting surfaces of the embedded electrical interconnects from a plane of the interface between the adjacent levels and effectively forming a barrier to flow of metal ions into the interface. In particular, during formation of the levels of interconnect routing, a layer of ILD is formed over a base substrate, which may be a semiconductor substrate or another level of interconnect routing. Trenches and/or vias are etched into the ILD, followed by deposition of an electrically-conductive material into the trenches and/or vias. Excess electrically-conductive material is removed through chemical and/or mechanical removal techniques to define the interconnect routing of embedded electrical interconnects. Wet etch techniques are then employed to etch electrically-conductive material from the exposed surfaces of the embedded electrical interconnects to thereby recess the embedded electrical interconnects within the ILD prior to forming additional layers thereon.
As a further feature to minimize TDDB attributable to migration of metal ions from the embedded electrical interconnects into the interface between adjacent levels of the interconnect routing, a barrier layer is often formed in the trenches and/or vias prior to depositing the electrically-conductive material in the trenches and/or vias. The barrier layer generally includes a barrier material such as tantalum nitride. A liner layer of liner material such as tantalum may be formed over the barrier layer prior to depositing the electrically-conductive material in the trenches and/or vias to further assist as a barrier to flow of metal ions into the interface. Recessing of the barrier layer and the liner layer within the substrate is desirable to promote electrical insulation of the embedded electrical interconnects and to further minimize TDDB. However, wet etch techniques that are employed to remove electrically-conductive material from the exposed surfaces of the embedded electrical interconnects do not etch the barrier material at the same rate as the electrically-conductive material. Further, dry etch techniques that are generally effective for etching tantalum nitride and tantalum also etch the oxide layer in the ILD at a high rate, which gives rise to reliability concerns in the integrated circuit by causing uneven topography, reducing the volume of ILD that separates the interconnect routing, and breaking down the oxide layer.
Accordingly, it is desirable to provide processes for forming integrated circuits having an embedded electrical interconnect within a substrate in which the embedded electrical interconnect is recessed within the substrate and that enables a barrier layer that is disposed between the substrate and the embedded electrical interconnect to also be effectively recessed within the substrate while minimizing etching of the oxide layer in the substrate. In addition, it is desirable to provide integrated circuits having a substrate with an embedded electrical interconnect recessed therein and with a barrier layer disposed between the embedded electrical interconnect and the substrate with the barrier layer also being recessed in the substrate. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.